The present invention relates to a non-contact current injection apparatus and method for testing electronic circuits, particularly linear circuits.
Devices for testing electronic circuits are known in the art. Two such devices are illustrated by U.S. Pat. Nos. 4,768,073 to Adams and 4,912,052 to Miyoshi et al.
The Adams patent relates to a technique for testing integrated circuits prior to separation from a processed wafer. Each circuit has photoreceivers coupled via metallization tracks to an adjacent circuit. The receivers are used for the input of high speed optical test signals. The response of each circuit to the test signals is monitored. The intercircuit coupling tracks are severed when the wafer is scribed to separate the individual circuits.
The Miyoshi et al. patent relates to a method and an apparatus for measuring and testing the electric characteristic of a semiconductor device in a non-contact fashion. In accordance with the Miyoshi et al. invention, an electron beam is used to induce a voltage on a semiconductor device which is to be tested. The electric characteristic of the semiconductor device is determined by the changes that occur, with lapse of time, of the induced voltage. Thus, an electron beam is irradiated to an object to be tested to induce a voltage; and, thereafter, changes in the induced voltage are examined. Then, the electric characteristic of the semiconductor device is measured and tested from the voltage thus induced, and the voltage measured thereafter.
Linear circuits, which are realized with bipolar linear application specific integrated circuits (ASICs), are fundamentally current mode devices. Linear arrays make use of a regularly occurring pattern of identical NPN and PNP transistors which are personalized with an interconnect for a specific circuit application. Once fabricated, malfunctioning or parametrically faulty devices require micro-probing techniques to isolate and evaluate faulty circuit sections. Typical micro-probing debugging involves the observation of output responses while injecting externally generated signals into the ASIC nodes with micro-probes.
With the shrinkage of device feature size, increased density, and additional layers of metallization interconnect, it is becoming more and more difficult to physically access such nodes for debugging purposes. In addition, the number of probes required becomes cumbersome and restricts the level of the testing effort.
Accordingly, it is an object of the present invention to provide an improved method and apparatus for testing electronic integrated circuits.
It is another object of the present invention to provide an improved testing method and apparatus, which injects a calibrated signal into an electronic component forming part of an electronic circuit through non-contact optical means.
It is a further object to provide an improved method and apparatus, commensurate with the above-listed objects, which can take advantage of the matched electrical and optical properties of the components of a linear array.
The above and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.